US 12,259,764 B2
Architecture for managing asynchronous resets in a system-on-a-chip
Kumar Abhishek, Bee Cave, TX (US); Neha Srivastava, New Delhi (IN); Yi Zheng, Austin, TX (US); and Nishant Kumar, Noida (IN)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on May 11, 2023, as Appl. No. 18/315,678.
Claims priority of application No. 202211070615 (IN), filed on Dec. 7, 2022.
Prior Publication US 2024/0192745 A1, Jun. 13, 2024
Int. Cl. G06F 1/24 (2006.01)
CPC G06F 1/24 (2013.01) 19 Claims
OG exemplary drawing
 
1. A reset generation circuit in a System-On-a-Chip (SoC), comprising:
a first reset generation circuit configured to enable a first reset signal based, at least in part, upon a clock signal and an indication to reset; and
a second reset generation circuit coupled to the first reset generation circuit, wherein the second reset generation circuit is configured to enable a second reset signal after the first reset signal is enabled, and wherein the first reset signal and the second reset signal are both provided to a component of the SoC, wherein the component of the SoC is a phase-locked-loop (PLL) comprising:
a PLL power-down circuit; and
a PLL control circuit coupled to the PLL power-down circuit.