US 12,259,746 B1
Dynamic clock scaling using compression and serialization
Pramod Bettagere Krishnamurthy, Bangalore (IN); and Sunil Raidurgam Venkat, Bangalore (IN)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Sunnyvale, CA (US)
Filed on Jul. 6, 2022, as Appl. No. 17/858,856.
Claims priority of provisional application 63/218,849, filed on Jul. 6, 2021.
Int. Cl. H04B 1/66 (2006.01); G06F 1/08 (2006.01); G06F 1/10 (2006.01); H03M 7/30 (2006.01)
CPC G06F 1/08 (2013.01) [G06F 1/10 (2013.01); H03M 7/30 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of transferring data from a first circuit block to a second circuit block, the method comprising:
sampling the data using a first clock signal during a first cycle;
compressing the sampled data at the first circuit block and using a compression ratio; and
responsive to a determination that the compression ratio is equal to or less than a threshold value:
selecting the compressed data for transmission to the second circuit block; and
selecting a second clock signal for sampling the data during a second cycle, wherein a phase of the second clock signal relative to a phase of the first clock signal is determined in accordance with the compression ratio.