US 12,259,662 B2
Methods for manufacturing semiconductor devices using MOIRÉ patterns
Woohyeok Jeong, Hwaseong-si (KR); Donghwan Kim, Pyeongtak-si (KR); Inchul Shin, Suwon-si (KR); Wonhyeok Jo, Daejeon (KR); Hyein Cho, Seoul (KR); and Seulgi Han, Seongnam-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Nov. 8, 2022, as Appl. No. 17/982,761.
Claims priority of application No. 10-2021-0155673 (KR), filed on Nov. 12, 2021.
Prior Publication US 2023/0152715 A1, May 18, 2023
Int. Cl. G03F 7/00 (2006.01); G01N 21/95 (2006.01); H01L 23/544 (2006.01); G02B 27/60 (2006.01)
CPC G03F 7/70633 (2013.01) [G01N 21/9501 (2013.01); G03F 7/70216 (2013.01); G03F 7/70683 (2013.01); H01L 23/544 (2013.01); G02B 27/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor device, comprising:
forming a first layer comprising a plurality of patterns, each of the plurality of patterns having a different respective pitch;
performing exposure and development to form an exposure pattern in a second layer at a layer different from the first layer;
determining whether or not a pitch shift of a part of exposure patterns formed by the performing the exposure and the development is within a tolerance range, using a Moiré pattern; and
performing etching for the second layer when the pitch shift of the part of exposure patterns is determined to be within the tolerance range,
wherein the performing the exposure and the development to form the second layer comprises:
forming a first exposure pattern corresponding to a key pattern having a first pitch,
forming a second exposure pattern corresponding to a cell pattern having a second pitch, and
forming a third exposure pattern corresponding to a middle pitch pattern having a third pitch between the first pitch and the second pitch.