US 12,259,624 B2
Display device
Atsushi Hirose, Kanagawa (JP)
Assigned to SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Kanagawa-ken (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Sep. 8, 2023, as Appl. No. 18/243,987.
Application 18/243,987 is a continuation of application No. 17/530,899, filed on Nov. 19, 2021, granted, now 11,754,896, issued on Sep. 12, 2023.
Application 17/530,899 is a continuation of application No. 16/790,351, filed on Feb. 13, 2020, granted, now 11,181,793, issued on Nov. 23, 2021.
Application 16/790,351 is a continuation of application No. 15/884,440, filed on Jan. 31, 2018, granted, now 10,564,499, issued on Feb. 18, 2020.
Application 15/884,440 is a continuation of application No. 15/585,926, filed on May 3, 2017, granted, now 9,885,932, issued on Feb. 6, 2018.
Application 15/585,926 is a continuation of application No. 15/368,969, filed on Dec. 5, 2016, granted, now 9,645,463, issued on May 9, 2017.
Application 15/368,969 is a continuation of application No. 13/313,244, filed on Dec. 7, 2011, granted, now 9,568,794, issued on Feb. 14, 2017.
Claims priority of application No. 2010-282635 (JP), filed on Dec. 20, 2010.
Prior Publication US 2024/0077773 A1, Mar. 7, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G02F 1/1362 (2006.01); G02F 1/1343 (2006.01); G02F 1/1368 (2006.01); G09G 3/36 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); G02F 1/136 (2006.01)
CPC G02F 1/136286 (2013.01) [G02F 1/134309 (2013.01); G02F 1/136213 (2013.01); G02F 1/136277 (2013.01); G02F 1/1368 (2013.01); G09G 3/3677 (2013.01); H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 27/1255 (2013.01); G02F 1/13606 (2021.01); G02F 1/13629 (2021.01); G02F 1/136295 (2021.01); G02F 2201/123 (2013.01); G02F 2202/10 (2013.01); G02F 2202/103 (2013.01); G09G 2330/021 (2013.01); H01L 29/78669 (2013.01); H01L 29/7869 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device comprising a pixel portion, the pixel portion comprising:
a scan line extending in a first direction and comprising a first region having an opening and a second region being adjacent to the first region of the scan line, a full width of the first region of the scan line being larger than a full width of the second region of the scan line in a top view;
a first wiring comprising a first part extending in parallel to the first direction and a second part adjacent to the first part, a full width of the first part of the first wiring being smaller than a full width of the second part of the first wiring in the top view;
a semiconductor film overlapping with the first region of the scan line;
a signal line comprising a first part extending in parallel to a second direction intersecting with the first direction, a second part extending in parallel to the first direction and overlapping with the opening of the scan line, and a third part being over and in contact with the semiconductor film;
a conductive layer having a first region being over and in contact with the semiconductor film and a second region overlapping with the first part and the second part of the first wiring; and
a pixel electrode over the first wiring and the conductive layer, the pixel electrode being in contact with the second region of the conductive layer,
wherein the semiconductor film comprises amorphous silicon,
wherein the first wiring comprises same materials of the scan line, and
wherein the conductive layer comprises same materials of the signal line.