US 12,259,623 B2
Array substrate and display device
Peirong Huo, Beijing (CN); Chao Liang, Beijing (CN); Peng Liu, Beijing (CN); Jingyi Xu, Beijing (CN); Bo Li, Beijing (CN); and Zhenhong Xiao, Beijing (CN)
Assigned to Ordos Yuansheng Optoelectronics Co., Ltd., Inner Mongolla (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 18/028,523
Filed by Ordos Yuansheng Optoelectronics Co., Ltd., Inner Mongolia (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Mar. 31, 2022, PCT No. PCT/CN2022/084245
§ 371(c)(1), (2) Date Mar. 25, 2023,
PCT Pub. No. WO2023/184292, PCT Pub. Date Oct. 5, 2023.
Prior Publication US 2024/0353720 A1, Oct. 24, 2024
Int. Cl. G02F 1/1362 (2006.01)
CPC G02F 1/136286 (2013.01) [G02F 1/136218 (2021.01)] 19 Claims
OG exemplary drawing
 
1. An array substrate comprising a display area and a non-display area that at least partially surrounds the display area, wherein the non-display area comprises at least two clock signal lines, a ratio of a spacing between two adjacent clock signal lines to a line width of the clock signal lines is greater than or equal to 3;
wherein the non-display area further comprises a ground protection line comprising at least one of a first ground protection line arranged on a side of the at least two clock signal lines close to the display area, a second ground protection line arranged between two adjacent clock signal lines, and a third ground protection line arranged on a side of the at least two clock signal lines away from the display area.