US 12,258,266 B2
Method and system for fabricating a MEMS device
Daesung Lee, San Jose, CA (US); and Alan Cuthbertson, San Jose, CA (US)
Assigned to InvenSense, Inc., San Jose, CA (US)
Filed by InvenSense, Inc., San Jose, CA (US)
Filed on Jul. 29, 2022, as Appl. No. 17/877,089.
Claims priority of provisional application 63/229,390, filed on Aug. 4, 2021.
Prior Publication US 2023/0037849 A1, Feb. 9, 2023
Int. Cl. B81C 1/00 (2006.01); B81B 3/00 (2006.01); B81B 7/00 (2006.01); B81B 7/02 (2006.01)
CPC B81C 1/00396 (2013.01) [B81B 3/0005 (2013.01); B81B 3/0081 (2013.01); B81B 7/0038 (2013.01); B81B 7/007 (2013.01); B81B 7/02 (2013.01); B81C 1/00269 (2013.01); B81C 1/00992 (2013.01); B81B 2201/0235 (2013.01); B81B 2201/0242 (2013.01); B81B 2203/0315 (2013.01); B81B 2203/04 (2013.01); B81B 2207/07 (2013.01); B81C 2201/0119 (2013.01); B81C 2201/013 (2013.01); B81C 2201/0132 (2013.01); B81C 2201/014 (2013.01); B81C 2201/0147 (2013.01); B81C 2201/0159 (2013.01); B81C 2201/016 (2013.01); B81C 2201/019 (2013.01); B81C 2201/0198 (2013.01); B81C 2201/112 (2013.01); B81C 2203/0109 (2013.01); B81C 2203/0118 (2013.01); B81C 2203/019 (2013.01); B81C 2203/035 (2013.01); B81C 2203/036 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A method comprising:
depositing a first intermetal dielectric (IMD) layer over a substrate;
depositing a first polysilicon layer over the first IMD layer;
depositing a second IMD layer over the first polysilicon layer;
etching a first portion of the second IMD layer to form a bumpstop region;
etching a second portion of the second IMD layer to expose a first portion of the first polysilicon layer;
subsequent to forming the bumpstop region and subsequent to exposing the first portion of the first polysilicon layer, depositing a second polysilicon layer over the second IMD layer and further over the first portion of the first polysilicon layer, wherein the second polysilicon layer directly connects to the first portion of the first polysilicon layer;
etching a portion of the second polysilicon layer to form a patterned second polysilicon layer and to expose a portion of the second IMD layer, wherein the etching the portion of the second polysilicon layer forms the bumpstop and a plurality of electrodes;
depositing a third IMD layer over the patterned second polysilicon layer and the exposed portion of the second IMD layer;
forming a via through the third IMD layer to expose a first portion of the patterned second polysilicon layer;
filling the via;
forming a bond layer over the via; and
etching a portion of the third IMD layer to expose a second portion of the patterned second polysilicon layer, wherein the second portion of the patterned second polysilicon layer is different from the first portion of the patterned second polysilicon layer.