CPC H04N 23/843 (2023.01) [H04N 9/67 (2013.01); H04N 23/80 (2023.01)] | 20 Claims |
1. An apparatus for processing image data, comprising:
a first demosaicing circuit configured to receive first image data in a first raw image format and to demosaic the first image data to generate first demosaiced image data;
a second demosaicing circuit configured to receive second image data in a second raw image format and to demosaic the second image data to generate second demosaiced image data, wherein the first demosaicing circuit and the second demosaicing circuit utilize a first shared set of line buffers for respectively generating the first demosaiced image data from the first image data and the second demosaiced image from the second image data;
a logic circuit configured to receive each of the first image data and the second image data from an image sensor, to provide the first image data to the first demosaicing circuit, and to provide the second image data to the second demosaicing circuit; and
a scaler circuit configured to perform post-processing on the first demosaiced image data and the second demosaiced image data using a second shared set of line buffers.
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