US 11,936,893 B2
Encoder, decoder, encoding method, and decoding method
Kiyofumi Abe, Osaka (JP); Takahiro Nishi, Nara (JP); Tadamasa Toma, Osaka (JP); and Yusuke Kato, Osaka (JP)
Assigned to PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA, Torrance, CA (US)
Filed by Panasonic Intellectual Property Corporation of America, Torrance, CA (US)
Filed on Nov. 15, 2021, as Appl. No. 17/526,098.
Application 17/526,098 is a continuation of application No. PCT/JP2020/020204, filed on May 21, 2020.
Claims priority of provisional application 62/850,682, filed on May 21, 2019.
Prior Publication US 2022/0078462 A1, Mar. 10, 2022
Int. Cl. H04N 19/46 (2014.01); H04N 19/184 (2014.01); H04N 19/65 (2014.01)
CPC H04N 19/46 (2014.11) [H04N 19/184 (2014.11); H04N 19/65 (2014.11)] 13 Claims
OG exemplary drawing
 
1. An encoder comprising:
memory; and
circuitry coupled to the memory and configured to:
encode a slice into one or more data access regions in a variable length encoding process; and
encode one or more offsets into a slice header, based on a flag written into a sequence header and a total number of the one or more data access regions, the one or more offsets each specifying a head position of a corresponding one of the one or more data access regions in a bitstream, wherein
when the flag indicates that the one or more offsets are to be encoded and the total number is at least two, the one or more offsets are encoded, and
the flag switches between encoding and not encoding the one or more offsets regardless of whether the total number is at least two.