US 11,936,887 B2
Encoder for encoding information of sub-bitstreams having mutually different frame rates
Virginie Drugeon, Darmstadt (DE); Tadamasa Toma, Osaka (JP); Takahiro Nishi, Nara (JP); Kiyofumi Abe, Osaka (JP); and Yusuke Kato, Osaka (JP)
Assigned to PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA, Torrance, CA (US)
Filed by Panasonic Intellectual Property Corporation of America, Torrance, CA (US)
Filed on Nov. 16, 2022, as Appl. No. 17/988,337.
Application 17/988,337 is a continuation of application No. 17/388,426, filed on Jul. 29, 2021, granted, now 11,553,195.
Application 17/388,426 is a continuation of application No. PCT/JP2020/005448, filed on Feb. 13, 2020.
Claims priority of provisional application 62/806,150, filed on Feb. 15, 2019.
Prior Publication US 2023/0080963 A1, Mar. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04N 19/31 (2014.01)
CPC H04N 19/31 (2014.11) 5 Claims
OG exemplary drawing
 
1. An encoder, comprising:
circuitry; and
memory coupled to the circuitry, wherein
the circuitry, in operation,
encodes identification information into a header of a bitstream including a plurality of sub-bitstreams respectively having mutually different frame rates, the identification information indicating a plurality of maximum temporal IDs which correspond to the plurality of sub-bitstreams, each of the plurality of maximum temporal IDs being a maximum identifier of one or more temporal layers related to a temporal scalability, and
for each of the plurality of sub-bitstreams, encodes level information indicating a conformance level of the sub-bitstream.