US 11,936,386 B2
Clock transfer circuit including a semiconductor device for compensating delay fluctuation
Soyeong Shin, Uiwang (KR); Yongjae Lee, Gwangju (KR); Jiheon Park, Seoul (KR); and Deog-Kyoon Jeong, Seoul (KR)
Assigned to SK hynix Inc., Icheon (KR); and Seoul National University R&DB Foundation, Seoul (KR)
Filed by SK hynix Inc., Icheon (KR); and Seoul National University R&DB Foundation, Seoul (KR)
Filed on Apr. 10, 2023, as Appl. No. 18/298,297.
Application 18/298,297 is a division of application No. 17/316,329, filed on May 10, 2021, granted, now 11,652,474.
Claims priority of application No. 10-2021-0000669 (KR), filed on Jan. 5, 2021.
Prior Publication US 2023/0246637 A1, Aug. 3, 2023
Int. Cl. H03K 5/135 (2006.01); H03K 5/00 (2006.01)
CPC H03K 5/135 (2013.01) [H03K 2005/00019 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A clock transfer circuit comprising:
a first stage circuit configured to produce an output signal that uses a second signaling technology from an input signal that uses a first signaling technology; and
a second stage circuit configured to produce a clock signal by delaying the output signal;
wherein the first stage circuit includes a semiconductor device configured to compensate for delay fluctuation caused by fluctuation of power supply voltage between a first power source and a second power source.