US 11,936,371 B1
Accurate reduced gate-drive current limiter
Satish Kumar Vangara, Woodley (GB); Antony Christopher Routledge, Basingstoke (GB); Gregory Szczeszynski, Nashua, NH (US); and Xiaowu Sun, Milford, NH (US)
Assigned to pSemi Corporation, San Diego, CA (US)
Filed by pSemi Corporation, San Diego, CA (US)
Filed on Oct. 4, 2022, as Appl. No. 17/959,904.
Int. Cl. H03K 17/08 (2006.01); H03K 5/08 (2006.01); H03K 17/082 (2006.01)
CPC H03K 17/0822 (2013.01) [H03K 5/086 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A gate control circuit for regulating a gate-drive voltage to a gate of a power FET, including:
(a) a source-follower circuit including a source-follower FET having a conduction channel configured to be coupled to the gate of the power FET, the gate control circuit configured to selectively apply at least a first gate-drive voltage or a second gate-drive voltage to the gate of the power FET such that a current flow through the power FET in an ON state is limited when the second gate-drive voltage is applied; and
(b) a feedback circuit coupled to a gate of the source-follower FET and configured to generate a feedback signal as a function of the current flow through the power FET and to regulate the second gate-drive voltage as a function of the generated feedback signal.