US 11,936,296 B2
Digital controller for high-performance multiphase VRM with current balancing and near-ideal transient response
Mor Mordechai Peretz, Lehavim (IL)
Assigned to B.G. NEGEV TECHNOLOGIES AND APPLICATIONS LTD., AT BEN-GURION UNIVERSITY, Beer Sheva (IL)
Appl. No. 17/632,389
Filed by B.G. NEGEV TECHNOLOGIES AND APPLICATIONS LTD., AT BEN-GURION UNIVERSITY, Beer Sheva (IL)
PCT Filed Aug. 4, 2020, PCT No. PCT/IL2020/050853
§ 371(c)(1), (2) Date Feb. 2, 2022,
PCT Pub. No. WO2021/024254, PCT Pub. Date Feb. 11, 2021.
Claims priority of provisional application 62/882,531, filed on Aug. 4, 2019.
Prior Publication US 2022/0294343 A1, Sep. 15, 2022
Int. Cl. H02M 3/158 (2006.01); H02M 1/00 (2006.01); H02M 3/156 (2006.01); H02M 3/157 (2006.01); H03M 1/50 (2006.01)
CPC H02M 3/157 (2013.01) [H02M 1/0003 (2021.05); H02M 3/1566 (2021.05); H02M 3/1584 (2013.01); H02M 3/1586 (2021.05); H03M 1/502 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A mixed-signal controller for controlling a multiphase average-current-mode voltage regulator having an output connected to a load, said controller comprises:
a. a digital voltage-sampling Analog-to-Digital Converter (ADC), based on Delay-Lines (DLs) and configured to obtain a sample of an output voltage signal and to convert said output voltage signal from analog to digital representation;
b. a digital current-sampling ADC, based on Delay-Lines (DLs) and configured to obtain a sample of a per-phase inductor current and to convert said inductor current from analog to digital representation;
c. a digital compensator, for voltage regulation, receiving as input a digital voltage error signal (ve[n]) created by a voltage loop and configured to generate a current reference signal, based on said digital voltage error signal;
d. a digital compensator for current regulation, for receiving as input a current error signal ie[n] and for generating a duty-ratio command signal, based on said digital current error signal;
e. a multiphase Digital Pulse Width Modulator (DPWM) , based on DLs, for receiving as input the duty-ratio command signal for each phase, for generating a pulse-width-modulated signal (for each phase) that is fed to the gates of transistors of said ADC, to thereby control per-phase currents and output voltage supplied to said load;
f. an analog front-end, for receiving differential measurements of the output voltage and the per-phase inductor current, where each signal is converted to a single-ended representation, such that single-ended signals are used for steady-state control via ADC measurement and a single-ended output voltage is used for transient detection and output voltage extremum detection during transient;
g. a Transient Suppression Unit (TSU), for receiving as input a digital indication signal from the analog front-end and for generating gating signals being fed to the gates of transistors of a converter during a transient event, to thereby control the current and voltage supplied to said load during said transient event;
h. a Phase Count Optimizer (PCO) unit for receiving as input a digital current reference signal and for generating, for each phase, an enable/disable control signal to a corresponding output tri-state buffer; and
i. an Active Voltage Positioning (AVP) unit for receiving as input a digital current reference signal and for generating a voltage loop compensator voltage reference signal.