US 11,935,960 B2
Integrated assemblies
Srinivas Pulugurtha, Boise, ID (US); Litao Yang, Boise, ID (US); Haitao Liu, Boise, ID (US); and Kamal M. Karda, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 13, 2022, as Appl. No. 17/864,244.
Application 17/864,244 is a division of application No. 17/017,426, filed on Sep. 10, 2020, granted, now 11,411,118.
Prior Publication US 2022/0352383 A1, Nov. 3, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/786 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H10B 12/00 (2023.01); H10B 53/20 (2023.01)
CPC H01L 29/78642 (2013.01) [H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/7869 (2013.01); H10B 12/31 (2023.02); H10B 53/20 (2023.02)] 20 Claims
OG exemplary drawing
 
1. Integrated memory, comprising:
a first series of first conductive structures; the first conductive structures extending along a first horizontal direction;
pillars of semiconductor material extending upwardly from the first conductive structures, the pillars having opposing sidewall surfaces extending a height of the pillar and having a uniform width along an entirety of the height; each of the pillars including a lower source/drain region, an upper source/drain region, and a channel region between the lower and upper source/drain regions; the lower source/drain regions being coupled with the first conductive structures;
insulative material adjacent an entirety of the sidewall surfaces of the pillars, the insulative material comprising ZrO where the chemical formula indicates primary constituents rather than a specific stoichiometry;
a second series of second conductive structures; the second conductive structures extending along a second horizontal direction which crosses the first direction; the second conductive structures comprising gating regions operatively proximate the channel regions and spaced from the channel regions by at least the insulative material; and
storage elements coupled with the upper source/drain regions.
 
15. Integrated memory comprising a transistor, the transistor comprising:
an active region including a post structure comprising semiconductor material, the post structure having opposing sidewalls extending along an entirety of a height of the post structure and including a channel region between a first source/drain region and a second source/drain region, an entirety of each of the first source/drain region and the second source/drain region being within the post structure; and
an insulative material adjacent the active region and extending along an entirety of the opposing sidewalls, the insulative material comprising ZrO where the chemical formula indicates primary constituents rather than a specific stoichiometry.