US 11,935,930 B2
Wrap-around-contact for 2D-channel gate-all-around field-effect-transistors
Julien Frougier, Albany, NY (US); Ruilong Xie, Niskayuna, NY (US); Kangguo Cheng, Schenectady, NY (US); Chanro Park, Clifton Park, NY (US); and Andrew Gaul, Halfmoon, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Nov. 30, 2021, as Appl. No. 17/456,947.
Prior Publication US 2023/0170394 A1, Jun. 1, 2023
Int. Cl. H01L 29/41 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/41741 (2013.01) [H01L 29/401 (2013.01); H01L 29/42392 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A vertical field-effect transistor (VFET) comprising:
a vertical channel;
a top conductive contact for one of a drain or source region, wherein a top end of the vertical channel wraps around the top conductive contact; and
a bottom conductive contact disposed on a substrate for one of a drain or source region, wherein a bottom end of the vertical channel wraps around the bottom conductive contact, and wherein the bottom end of the vertical channel and the bottom conductive contact both directly contact the substrate.