US 11,935,890 B2
Method for forming integrated semiconductor device with 2D material layer
Cheng-Yi Peng, Taipei (TW); Chun-Chieh Lu, Taipei (TW); Meng-Hsuan Hsiao, Hsinchu (TW); Ling-Yen Yeh, Hsinchu (TW); Carlos H. Diaz, Los Altos Hills, CA (US); and Tung-Ying Lee, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Apr. 11, 2022, as Appl. No. 17/718,182.
Application 17/718,182 is a division of application No. 16/940,258, filed on Jul. 27, 2020, granted, now 11,302,695.
Application 16/940,258 is a division of application No. 16/133,028, filed on Sep. 17, 2018, granted, now 10,727,230, issued on Jul. 28, 2020.
Claims priority of provisional application 62/592,991, filed on Nov. 30, 2017.
Prior Publication US 2022/0238523 A1, Jul. 28, 2022
Int. Cl. H01L 27/092 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 23/538 (2006.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H04L 9/40 (2022.01); H04L 67/303 (2022.01); H04L 67/306 (2022.01)
CPC H01L 27/0924 (2013.01) [H01L 21/0228 (2013.01); H01L 21/76897 (2013.01); H01L 23/53295 (2013.01); H01L 23/5384 (2013.01); H01L 27/1248 (2013.01); H01L 29/0665 (2013.01); H01L 29/0847 (2013.01); H01L 29/41733 (2013.01); H01L 29/42356 (2013.01); H01L 29/45 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/778 (2013.01); H01L 29/7851 (2013.01); H01L 29/786 (2013.01); H01L 29/78681 (2013.01); H01L 29/78684 (2013.01); H04L 63/0853 (2013.01); H04L 67/303 (2013.01); H04L 67/306 (2013.01); H01L 29/41791 (2013.01); H01L 2029/7858 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a first inter-layer dielectric (ILD) layer over a semiconductor device that includes a first transistor structure;
forming a two-dimensional (2D) material layer over and in contact with the first ILD layer;
patterning the 2D material layer to form a channel layer of a second transistor structure;
forming a source electrode and a drain electrode of the second transistor structure over the patterned 2D material layer and laterally spaced apart from each other;
forming a gate dielectric layer of the second transistor structure over the patterned 2D material layer, the source electrode and the drain electrode; and
forming a gate electrode of the second transistor structure over the gate dielectric layer and laterally between the source electrode and the drain electrode.