CPC H01L 27/0924 (2013.01) [H01L 21/0228 (2013.01); H01L 21/76897 (2013.01); H01L 23/53295 (2013.01); H01L 23/5384 (2013.01); H01L 27/1248 (2013.01); H01L 29/0665 (2013.01); H01L 29/0847 (2013.01); H01L 29/41733 (2013.01); H01L 29/42356 (2013.01); H01L 29/45 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/778 (2013.01); H01L 29/7851 (2013.01); H01L 29/786 (2013.01); H01L 29/78681 (2013.01); H01L 29/78684 (2013.01); H04L 63/0853 (2013.01); H04L 67/303 (2013.01); H04L 67/306 (2013.01); H01L 29/41791 (2013.01); H01L 2029/7858 (2013.01)] | 20 Claims |
1. A method comprising:
forming a first inter-layer dielectric (ILD) layer over a semiconductor device that includes a first transistor structure;
forming a two-dimensional (2D) material layer over and in contact with the first ILD layer;
patterning the 2D material layer to form a channel layer of a second transistor structure;
forming a source electrode and a drain electrode of the second transistor structure over the patterned 2D material layer and laterally spaced apart from each other;
forming a gate dielectric layer of the second transistor structure over the patterned 2D material layer, the source electrode and the drain electrode; and
forming a gate electrode of the second transistor structure over the gate dielectric layer and laterally between the source electrode and the drain electrode.
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