US 11,935,835 B2
Methods of manufacturing semiconductor devices
Hyo-Jin Kim, Bucheon-si (KR); Chang-Hwa Kim, Hwaseong-si (KR); Hwi-Chan Jun, Yongin-si (KR); Chul-Hong Park, Seongnam-si (KR); Jae-Seok Yang, Hwaseong-si (KR); and Kwan-Young Chun, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Dec. 14, 2020, as Appl. No. 17/120,616.
Application 17/120,616 is a division of application No. 16/217,220, filed on Dec. 12, 2018, granted, now 10,886,227.
Application 16/217,220 is a division of application No. 15/497,283, filed on Apr. 26, 2017, granted, now 10,177,093, issued on Jan. 8, 2019.
Claims priority of application No. 10-2016-0128085 (KR), filed on Oct. 5, 2016.
Prior Publication US 2021/0098377 A1, Apr. 1, 2021
Int. Cl. H01L 23/535 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 21/84 (2006.01); H01L 27/088 (2006.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 23/535 (2013.01) [H01L 21/76826 (2013.01); H01L 21/76829 (2013.01); H01L 21/76895 (2013.01); H01L 21/76897 (2013.01); H01L 21/823431 (2013.01); H01L 21/823475 (2013.01); H01L 21/845 (2013.01); H01L 27/088 (2013.01); H01L 27/0886 (2013.01); H01L 27/1211 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/41791 (2013.01); H01L 29/66545 (2013.01); H01L 29/785 (2013.01); H01L 21/76831 (2013.01); H01L 21/76889 (2013.01); H01L 21/823481 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
forming transistors on a substrate such that each of the transistors includes a gate structure and a source/drain layer adjacent thereto;
forming a first insulating interlayer on the substrate to cover the transistors;
forming first contact plugs and a second contact plug through the first insulating interlayer to contact the source/drain layers, respectively;
forming a second insulating interlayer on the first insulating interlayer, and the first and second contact plugs;
forming first and second openings through the first and second insulating interlayers such that the first opening exposes one of the gate structures and the second opening commonly exposes at least one of the gate structures and the second contact plug adjacent thereto;
forming a first insulating spacer on a sidewall of the first opening; and
forming third and fourth contact plugs in the first and second openings, respectively.