US 11,935,781 B2
Integrated circuit structure with backside dielectric layer having air gap
Che-Lun Chang, Hsinchu (TW); Wei-Yang Lee, Taipei (TW); Chia-Pin Lin, Xinpu Township (TW); and Yuan-Ching Peng, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 28, 2022, as Appl. No. 17/815,669.
Application 17/815,669 is a continuation of application No. 17/149,918, filed on Jan. 15, 2021, granted, now 11,450,559.
Claims priority of provisional application 63/017,141, filed on Apr. 29, 2020.
Prior Publication US 2022/0367243 A1, Nov. 17, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H01L 21/306 (2006.01); H01L 21/762 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 21/7682 (2013.01) [H01L 21/7624 (2013.01); H01L 21/76804 (2013.01); H01L 21/76805 (2013.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01); H01L 29/41733 (2013.01); H01L 29/66439 (2013.01); H01L 29/66742 (2013.01); H01L 21/30604 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/42392 (2013.01); H01L 29/45 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device, the method comprising:
etching a recess in a substrate, wherein the substrate comprises a first material;
forming a plug in the recess in the substrate, wherein the plug comprises a second material different than the first material;
forming an epitaxial structure over the plug;
forming a gate structure on a first side of the substrate adjacent epitaxial structure;
removing at least a portion of a backside of the substrate to expose the plug;
forming a dielectric layer over the plug, the dielectric layer having an air gap therein;
removing the plug to form a backside via opening through the dielectric layer; and
forming a backside via in the backside via opening, wherein the backside via is electrically coupled to the epitaxial structure.