CPC H01L 21/30625 (2013.01) [H01L 21/0335 (2013.01); H01L 21/0337 (2013.01); H01L 21/0338 (2013.01); H01L 21/30604 (2013.01); H01L 21/3086 (2013.01); H01L 21/3088 (2013.01); H01L 23/564 (2013.01); H01L 2924/0002 (2013.01)] | 8 Claims |
1. A method used during fabrication of a semiconductor device, comprising:
providing a layer to be etched;
forming a sacrificial patterning layer over the layer to be etched, wherein the sacrificial patterning layer comprises a plurality of segmented portions having at least first and second cross sectional sidewalls;
forming a plurality of sacrificial first spacers, with one spacer formed on each sidewall of each segmented portion of the sacrificial patterning layer;
removing the sacrificial patterning layer;
forming a conformal second spacer layer over the plurality of sacrificial first spacers;
removing a portion of the conformal second spacer layer to form a plurality of second spacers on the sacrificial first spacers, wherein the second spacers have different elevational thicknesses;
subsequent to forming the second spacers, removing the sacrificial first spacers; and
etching the layer to be etched using the second spacers as a pattern.
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