US 11,935,579 B2
Protection circuit and memory
Geyan Liu, Hefei (CN); and Yinchuan Gu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Oct. 21, 2021, as Appl. No. 17/451,818.
Application 17/451,818 is a continuation of application No. PCT/CN2021/105066, filed on Jul. 7, 2021.
Claims priority of application No. 202110069469.0 (CN), filed on Jan. 19, 2021.
Prior Publication US 2022/0230673 A1, Jul. 21, 2022
Int. Cl. G11C 7/00 (2006.01); G11C 11/4078 (2006.01); G11C 29/08 (2006.01); H01L 27/02 (2006.01)
CPC G11C 11/4078 (2013.01) [G11C 29/08 (2013.01); H01L 27/0251 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A protection circuit applied in a chip, comprising:
a first protection unit, wherein the first protection unit is configured to receive a first input signal and a control signal, and is configured to output a first output signal; and
a first element to be protected comprising a first P-type transistor, wherein a gate of the first P-type transistor is configured to receive the first output signal;
wherein when the chip enters a burn-in test, the first output signal is a high-level signal,
wherein the protection circuit further comprises: a second protection unit and a second element to be protected,
wherein the second protection unit is configured to receive a second input signal and the control signal, and is configured to output a second output signal;
the second element to be protected comprises a second P-type transistor, and a gate of the second P-type transistor is configured to receive the second output signal; and
when the chip enters the burn-in test, the second output signal is a high-level signal.