| CPC G06Q 40/04 (2013.01) | 20 Claims |
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1. A field programmable gate array (FPGA) based matching engine comprising:
a network interface configured to receive data packets containing proposed transactions, wherein the proposed transactions are respectively associated with transaction subjects, and wherein the network interface identifies network addresses in initial sequences of bits in each of the data packets in parallel to receiving respective further sequences of bits in each of the data packets;
state memory containing information related to the proposed transactions;
policy memory containing policies to be applied to the proposed transactions;
transaction validation circuitry configured to: receive the proposed transactions from the network interface and validate the proposed transactions based on their identified network addresses, their related information from the state memory, and the policies, wherein the transaction validation circuitry is further configured to discard any data packets containing proposed transactions that do not conform to the policies;
pending transaction memory configured to store proposed transactions that were validated in one or more tables; and
matching algorithm circuitry configured to read at least some of the proposed transactions from the one more of tables and match pairs of pending transactions according to pre-determined criteria, wherein the matching algorithm circuitry is subject to a 50-300 nanosecond random delay when matching the pairs of the pending transactions.
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