US 11,934,824 B2
Methods for performing processing-in-memory operations, and related memory devices and systems
Dmitri Yudanov, Cordova, CA (US); Sean S. Eilert, Penryn, CA (US); Sivagnanam Parthasarathy, Carlsbad, CA (US); Shivasankar Gunasekaran, Folsom, CA (US); and Ameen D. Akel, Rancho Cordova, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 6, 2020, as Appl. No. 16/841,222.
Claims priority of provisional application 62/896,228, filed on Sep. 5, 2019.
Prior Publication US 2021/0072987 A1, Mar. 11, 2021
Int. Cl. G06F 9/30 (2018.01); G06F 7/544 (2006.01)
CPC G06F 9/3001 (2013.01) [G06F 7/5443 (2013.01); G06F 9/30032 (2013.01); G06F 9/30043 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
loading a first number of bits from a first array into a sequencer of a memory device, each bit of the first number of bits having a first state or a second state;
loading, from a second array in a bit-parallel manner, a second number of groups of bits into a third array, each bit of the second number of groups of bits having the first state or the second state;
multiplying each group of bits of the second number of groups of bits by each bit of the first number of bits to generate a number of scaled rows; and
summing, along associated bit positions, the number of scaled rows to generate an output row.