US 11,934,705 B2
Truth table extension for stacked memory systems
Joseph T. Pawlowski, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 19, 2023, as Appl. No. 18/099,051.
Application 18/099,051 is a continuation of application No. 17/127,785, filed on Dec. 18, 2020, granted, now 11,561,731.
Claims priority of provisional application 62/953,819, filed on Dec. 26, 2019.
Prior Publication US 2023/0161508 A1, May 25, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01); H01L 25/0652 (2013.01); H01L 25/18 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A logic die for a storage device, the logic die comprising:
a first interface to communicate with a stack of memory die of the storage device;
a second interface configured to couple with a host device;
a second memory accessible from the second interface; and
processing circuitry configured to:
initiate a first operation for the stack of memory die in response to a first request from the host device, wherein the first request uses a first command/address bus of the second interface to identify the first operation;
initiate a second operation for the stack of memory die in response to a second request from the host device, wherein the second request uses a second command/address bus of the second interface to identify the second operation as a read operation or a write operation; and
initiate a third operation for the second memory in response to a third request from the host device, wherein the third request uses both the first command/address bus and the second command/address bus to identify the third operation for the second memory.