US 11,934,698 B2
Process isolation for a processor-in-memory (“PIM”) device
Sooraj Puthoor, Austin, TX (US); Muhammad Amber Hassaan, San Marcos, TX (US); Ashwin Aji, Santa Clara, CA (US); Michael L. Chu, Santa Clara, CA (US); and Nuwan Jayasena, Santa Clara, CA (US)
Assigned to ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed on Dec. 20, 2021, as Appl. No. 17/556,503.
Prior Publication US 2023/0195375 A1, Jun. 22, 2023
Int. Cl. G06F 3/06 (2006.01); G06F 7/575 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0622 (2013.01); G06F 3/0631 (2013.01); G06F 3/0656 (2013.01); G06F 3/0679 (2013.01); G06F 7/575 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a processor;
memory operatively coupled to the processor; and
a processing-in-memory (PIM) device, wherein the processor comprises one or more processing cores executing a plurality of processes and the memory comprises computer program instructions that are executable by the processor to:
receive, from a process of the plurality of processes, a call requesting ownership of the PIM device, the call including one or more PIM configuration parameters and a process identifier (PID) of the process requesting the ownership; and
grant the ownership of the PIM device to the process requesting the ownership, including configuring the PIM device according to the one or more PIM configuration parameters and recording the PID of the process requesting the ownership.