US 11,934,692 B2
Write booster buffer and hibernate
Luca Porzio, Casalnuovo (IT); and Deping He, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 20, 2021, as Appl. No. 17/645,265.
Prior Publication US 2023/0195370 A1, Jun. 22, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0656 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0634 (2013.01); G06F 3/0653 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory system; and
a controller coupled with the memory system, wherein the controller is configured to cause the apparatus to:
initiate, at the memory system, a first operation to enter a first power mode having a lower power consumption than a second power mode;
determine whether a total bytes written to the memory system satisfies a threshold;
determine whether a quantity of data stored in a buffer of single-level cells associated with write booster information satisfies a second threshold based at least in part on initiating the first operation to enter the first power mode, wherein determining whether the quantity of data satisfies the second threshold is based at least in part on determining whether the total bytes written satisfies the threshold;
determine whether to perform a second operation to transfer the quantity of data stored in the buffer of single-level cells to a portion of memory comprising multiple level cells based at least in part on determining whether the quantity of data satisfies the second threshold; and
enter the first power mode based at least in part on determining to perform the second operation to transfer the quantity of data from the buffer to the portion of memory.