US 11,934,661 B1
Partitioning responsive to processors having a disparate number of memory modules
Gary D. Cudak, Raleigh, NC (US); Mehul Shah, Austin, TX (US); Pravin S. Patel, Cary, NC (US); and James Parsonese, Cary, NC (US)
Filed by Lenovo Enterprise Solutions (Singapore) Pte Ltd., Singapore (SG)
Filed on Dec. 22, 2022, as Appl. No. 18/087,105.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0614 (2013.01) [G06F 3/0644 (2013.01); G06F 3/067 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computer program product comprising a non-volatile computer readable medium and non-transitory program instructions embodied therein, the program instructions being configured to be executable by a processor of a baseboard management controller in a multi-processor system to cause the processor to perform operations comprising:
detecting a number of memory modules connected to each of a plurality of central processing units in the multi-processor system during boot;
initiating operation of the multi-processor system as a single unified node in response to each of the plurality of central processing units being connected to an equal number of memory modules; and
initiating partitioning of the multi-processor system into a first partitioned node and a second partitioned node in response to a first set of one or more of the central processing units each being connected to a first number of memory modules and a second set of one or more of the central processing units each being connected to a second number of memory modules that is different than the first number of memory modules.