US 11,934,326 B2
Memory with improved command/address bus utilization
Debra M. Bell, Boise, ID (US); Vaughn N. Johnson, Boise, ID (US); Kyle Alexander, Boise, ID (US); Gary L. Howe, Allen, TX (US); Brian T. Pecha, Boise, ID (US); and Miles S. Wiscombe, Boise, ID (US)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Aug. 6, 2022, as Appl. No. 17/882,550.
Application 17/882,550 is a continuation of application No. 17/062,484, filed on Oct. 2, 2020, granted, now 11,409,674.
Prior Publication US 2022/0391334 A1, Dec. 8, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/16 (2006.01); G11C 11/406 (2006.01); G11C 11/4096 (2006.01)
CPC G06F 13/1668 (2013.01) [G11C 11/40611 (2013.01); G11C 11/40618 (2013.01); G11C 11/4096 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory array,
wherein the apparatus is configured to receive, from a command bus, a command as a corresponding plurality of bits, wherein the plurality of bits includes (a) a first set of bits usable to instruct the apparatus to execute an access operation and (b) a second set of bits usable to instruct the apparatus to execute a refresh operation,
wherein the apparatus is configured, in response to receiving the first set of bits of the command, to execute the access operation on a first portion of the memory array, and
wherein, in addition to executing the access operation in response to the first set of bits of the command, the apparatus is further configured, in response to the second set of bits of the command, to execute the refresh operation to refresh a second portion of the memory array.