US 11,934,325 B2
Memory device interface communicating with set of data bursts corresponding to memory dies via dedicated portions for command processing
Luigi Pilolli, L'Aquila (IT)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on May 26, 2022, as Appl. No. 17/825,632.
Application 17/825,632 is a continuation of application No. 17/081,483, filed on Oct. 27, 2020, granted, now 11,347,663, issued on May 31, 2022.
Prior Publication US 2022/0283965 A1, Sep. 8, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/00 (2006.01); G06F 13/16 (2006.01); G06F 13/22 (2006.01); G06F 13/28 (2006.01); G06F 13/40 (2006.01)
CPC G06F 13/1668 (2013.01) [G06F 13/1615 (2013.01); G06F 13/22 (2013.01); G06F 13/28 (2013.01); G06F 13/4068 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a set of memory dies; and
a processing device, operatively coupled to the set of memory dies via an interface comprising a first portion and a second portion, the processing device to perform operations comprising:
communicating a set of commands associated with the set of memory dies via the first portion of the interface; and
causing communication of a set of data communications to the set of memory dies via the second portion of the interface, wherein one or more of the set of commands is communicated via the first portion of the interface concurrently with one or more of the set of data communications.