US 11,934,310 B2
Zero bits in L3 tags
Douglas Raye Reed, Austin, TX (US); Al Loper, Austin, TX (US); and Terry Parks, Austin, TX (US)
Assigned to CENTAUR TECHNOLOGY, INC., Austin, TX (US)
Filed by CENTAUR TECHNOLOGY, INC., Austin, TX (US)
Filed on Jan. 21, 2022, as Appl. No. 17/581,162.
Prior Publication US 2023/0236972 A1, Jul. 27, 2023
Int. Cl. G06F 12/0811 (2016.01); G06F 12/0817 (2016.01); G06F 12/0853 (2016.01); G06F 12/0891 (2016.01)
CPC G06F 12/0811 (2013.01) [G06F 12/0817 (2013.01); G06F 12/0853 (2013.01); G06F 12/0891 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A microprocessor, comprising:
plural cores, each of the cores comprising a level 1 (L1) cache and a level 2 (L2) cache; and
a shared level 3 (L3) cache comprising plural L3 tag array entries, wherein a first portion of the plural L3 tag array entries is associated with data in the shared L3 cache and a second portion of the plural L3 tag array entries is decoupled from data in the shared L3 cache and available in the L2 cache of one of the plural cores, wherein each L3 tag array entry comprises tag information and data zero information, the data zero information indicating whether any data associated with the tag information is known to be zero or not.