US 11,934,266 B2
Memory compaction management in memory devices
Vamsi Pavan Rayaprolu, Santa Clara, CA (US); Mustafa N. Kaynak, San Diego, CA (US); Sivagnanam Parthasarathy, Carlsbad, CA (US); Patrick Khayat, San Diego, CA (US); Sampath Ratnam, San Jose, CA (US); Kishore Kumar Muchherla, Fremont, CA (US); Jiangang Wu, Milpitas, CA (US); and James Fitzpatrick, Laguna Niguel, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 7, 2022, as Appl. No. 17/859,468.
Claims priority of provisional application 63/347,823, filed on Jun. 1, 2022.
Prior Publication US 2023/0393938 A1, Dec. 7, 2023
Int. Cl. G11C 29/00 (2006.01); G06F 11/07 (2006.01); G06F 11/10 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/076 (2013.01); G06F 11/0772 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, to perform operations comprising:
selecting a source set of memory cells of the memory device, wherein the source set of memory cells are configured to store a first number of bits per memory cell;
performing a data integrity check on the source set of memory cells to obtain a data integrity metric value;
determining whether the data integrity metric value satisfies a threshold criterion; and
responsive to determining that the data integrity metric value fails to satisfy the threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell, wherein the second number of bits per memory cells is greater than the first number of bits per memory cell.