US 11,934,240 B2
PMU-side thermal control
Inder M. Sodhi, Palo Alto, CA (US); Achmed R. Zahir, Menlo Park, CA (US); Carmel Yamberger, Kfar-Saba (IL); Daniele Perretta, Redwood City, CA (US); Jan Krellner, Rancho Mission Viejo, CA (US); Ron Neuman, Ramat Hasharon (IL); James S. Ismail, Sunnyvale, CA (US); and Keith Cox, Sunnyvale, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on May 18, 2022, as Appl. No. 17/664,000.
Prior Publication US 2023/0376091 A1, Nov. 23, 2023
Int. Cl. G06F 1/28 (2006.01); G06F 1/20 (2006.01); G06F 11/30 (2006.01)
CPC G06F 1/206 (2013.01) [G06F 1/28 (2013.01); G06F 11/3058 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
processor circuitry included on a first chip;
a power converter configured to power the processor circuitry via one or more rails;
power management unit (PMU) circuitry, on a second chip, configured to:
implement one or more thermal control loops that operate on thermal data from the power converter as an input; and
output a reduction alert signal to the processor circuitry, via an inter-chip communications interconnect coupled to the first and second chips, based on the thermal data;
wherein the processor circuitry is configured to reduce its processing activity in response to the reduction alert signal.