CPC G06F 1/206 (2013.01) [G06F 1/28 (2013.01); G06F 11/3058 (2013.01)] | 20 Claims |
1. An apparatus, comprising:
processor circuitry included on a first chip;
a power converter configured to power the processor circuitry via one or more rails;
power management unit (PMU) circuitry, on a second chip, configured to:
implement one or more thermal control loops that operate on thermal data from the power converter as an input; and
output a reduction alert signal to the processor circuitry, via an inter-chip communications interconnect coupled to the first and second chips, based on the thermal data;
wherein the processor circuitry is configured to reduce its processing activity in response to the reduction alert signal.
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