US 11,933,844 B2
Path based controls for ATE mode testing of multicell memory circuit
Wilson Pradeep, Bangalore (IN); and Prakash Narayanan, Bangalore (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on May 26, 2021, as Appl. No. 17/330,653.
Application 17/330,653 is a continuation of application No. 16/185,660, filed on Nov. 9, 2018, granted, now 11,047,910.
Claims priority of provisional application 62/611,676, filed on Dec. 29, 2017.
Claims priority of provisional application 62/611,704, filed on Dec. 29, 2017.
Prior Publication US 2021/0278459 A1, Sep. 9, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G01R 31/3177 (2006.01); G01R 31/317 (2006.01); G06F 11/10 (2006.01); G11C 29/36 (2006.01); G11C 29/42 (2006.01); G11C 29/56 (2006.01)
CPC G01R 31/3177 (2013.01) [G01R 31/31718 (2013.01); G01R 31/31724 (2013.01); G06F 11/1048 (2013.01); G06F 11/1068 (2013.01); G11C 29/36 (2013.01); G11C 29/42 (2013.01); G11C 29/56004 (2013.01); G11C 2029/3602 (2013.01); G11C 2029/5602 (2013.01)] 20 Claims
OG exemplary drawing
 
19. A method, comprising:
receiving a control signal to control data access to data paths that are operatively coupled between memory and an external device;
generating an output signal that indicates a selected data path in response to the control signal;
enabling at least one clock gate in a gating circuit to control the selected data path are to be accessed by the external device in response to the output signal, wherein the gating circuit comprises a first set of logic gates, a second set of logic gates, and a decoder, wherein an output of the first set of the logic gates is coupled to an input of the decoder, wherein an output of the decoder are coupled to an input of the second set of logic gates, wherein an output of the second set of logic gates is operatively coupled to the memory; and
accessing the memory, by the external device, via the selected data path enabled by the enabling.