US 12,256,648 B2
Seal structures
Chun Yu Chen, Hsinchu (TW); and Yen Lian Lai, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 20, 2023, as Appl. No. 18/355,550.
Application 18/355,550 is a continuation of application No. 17/465,556, filed on Sep. 2, 2021, granted, now 11,728,338, issued on Aug. 15, 2023.
Claims priority of provisional application 63/220,112, filed on Jul. 9, 2021.
Prior Publication US 2023/0397502 A1, Dec. 7, 2023
Int. Cl. H10N 50/80 (2023.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01)
CPC H10N 50/80 (2023.02) [H10B 61/22 (2023.02); H10N 50/01 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) chip, comprising:
a device region;
an inner ring surrounding the device region; and
an outer ring surrounding the inner ring,
wherein, from a top view, the inner ring has an octagonal shape and the outer ring has a rectangular shape,
wherein the outer ring and the inner ring define four corner areas between outer corners of the inner ring and an inner corner of the outer ring,
wherein each of the four corner areas comprises:
an active region comprising a channel region and a source/drain region,
a gate structure over the channel region of the active region, and
a source/drain contact over the source/drain region of the active region,
wherein the source/drain contact continuously extends from a first edge to a second edge of each of the four corner areas.