US 12,256,647 B2
Embedded MRAM fabrication process for ion beam etching with protection by top electrode spacer
Jun-Yao Chen, Hsinchu (TW); Harry-Hak-Lay Chuang, Hsinchu (TW); and Hung Cho Wang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 2, 2023, as Appl. No. 18/311,191.
Application 18/311,191 is a continuation of application No. 17/342,464, filed on Jun. 8, 2021, granted, now 11,659,775.
Application 17/342,464 is a continuation of application No. 16/672,110, filed on Nov. 1, 2019, granted, now 11,063,208, issued on Jul. 13, 2021.
Claims priority of provisional application 62/868,637, filed on Jun. 28, 2019.
Prior Publication US 2023/0270018 A1, Aug. 24, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10N 50/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01); H10N 50/85 (2023.01)
CPC H10N 50/80 (2023.02) [H10N 50/01 (2023.02); H10N 50/85 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A structure, comprising:
a semiconductor substrate;
a first structure over the semiconductor substrate;
a first electrode directly and completely on a first surface of the first structure; and
a first sidewall spacer on the first surface of the first structure and laterally adjacent to a sidewall of the first electrode.