US 12,256,646 B2
Memory device and method of fabricating the same
Yen-Lin Huang, Menlo Park, CA (US); Ming-Yuan Song, Hsinchu (TW); Chien-Min Lee, Hsinchu County (TW); Nuo Xu, San Jose, CA (US); and Shy-Jay Lin, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 30, 2022, as Appl. No. 17/827,998.
Prior Publication US 2023/0389439 A1, Nov. 30, 2023
Int. Cl. H10N 50/10 (2023.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01); H10N 50/85 (2023.01)
CPC H10N 50/10 (2023.02) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 61/22 (2023.02); H10N 50/01 (2023.02); H10N 50/80 (2023.02); H10N 50/85 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a substrate;
a spin-orbit torque layer disposed on the substrate;
a magnetic tunneling junction (MTJ) film stack formed over the spin-orbit torque layer and on the substrate;
a connecting via disposed on and electrically connected to the MTJ film stack; and
a shielding structure laterally surrounding the MTJ film stack and disposed on the spin-orbit torque layer, wherein the shielding structure comprises a first dielectric layer, a high magnetic permeability layer and a second dielectric layer, the first dielectric layer is in contact with the spin-orbit torque layer and the MTJ film stack, and the high magnetic permeability layer is sandwiched between the first dielectric layer and the second dielectric layer.