US 12,256,593 B2
Display device and method of manufacturing the same
Jaybum Kim, Seoul (KR); Eoksu Kim, Seoul (KR); Kyoungseok Son, Seoul (KR); Junhyung Lim, Seoul (KR); and Jihun Lim, Hwaseong-si (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Gyeonggi-Do (KR)
Filed by SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed on Dec. 2, 2022, as Appl. No. 18/073,870.
Application 18/073,870 is a continuation of application No. 17/082,459, filed on Oct. 28, 2020, granted, now 11,575,100.
Application 17/082,459 is a continuation of application No. 16/911,525, filed on Jun. 25, 2020, granted, now 10,854,837, issued on Dec. 1, 2020.
Application 16/911,525 is a continuation of application No. 16/836,005, filed on Mar. 31, 2020, granted, now 10,790,467, issued on Sep. 29, 2020.
Application 16/836,005 is a continuation of application No. 16/459,060, filed on Jul. 1, 2019, granted, now 10,673,008, issued on Jun. 2, 2020.
Application 16/459,060 is a continuation of application No. 15/657,369, filed on Jul. 24, 2017, granted, now 10,340,472, issued on Jul. 2, 2019.
Claims priority of application No. 10-2016-0113445 (KR), filed on Sep. 2, 2016.
Prior Publication US 2023/0099080 A1, Mar. 30, 2023
Int. Cl. H10K 50/805 (2023.01); G09G 3/32 (2016.01); G09G 3/3233 (2016.01); H10B 10/00 (2023.01); H10K 50/30 (2023.01); H10K 59/12 (2023.01); H10K 59/121 (2023.01); H10K 71/00 (2023.01); H10K 77/10 (2023.01)
CPC H10K 50/805 (2023.02) [G09G 3/32 (2013.01); G09G 3/3233 (2013.01); H10B 10/125 (2023.02); H10K 59/1213 (2023.02); H10K 77/10 (2023.02); G09G 2300/0426 (2013.01); G09G 2300/0814 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2300/0866 (2013.01); G09G 2310/0245 (2013.01); G09G 2310/0262 (2013.01); H10K 50/30 (2023.02); H10K 59/1201 (2023.02); H10K 59/1216 (2023.02); H10K 71/621 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A display device comprising:
a base substrate;
a first transistor above the base substrate and comprising a first channel area below a first insulation layer and a first gate above the first insulation layer and below a second insulation layer;
a second transistor above the base substrate and comprising a second gate above the first insulation layer and below the second insulation layer, a second channel area above the second insulation layer and a third gate above the first and the second insulation layers and electrically connected to the second gate;
a third transistor above the base substrate and comprising a third channel area below the first insulation layer and a fourth gate above the first insulation layer and below the second insulation layer; and
a light emitting diode above the second insulation layer,
wherein the first transistor is electrically connected to the second transistor through a conductive pattern,
the first transistor is electrically connected to the third transistor, and
the first channel area comprises a polysilicon semiconductor and the second channel area comprises an oxide semiconductor.