US 12,256,586 B2
Current control systems and methods
Sean E. Doris, San Francisco, CA (US); Warren B. Jackson, San Francisco, CA (US); and Adrien Pierre, Berkeley, CA (US)
Assigned to Xerox Corporation, Norwalk, CT (US)
Filed by Palo Alto Research Center Incorporated, Palo Alto, CA (US)
Filed on Mar. 22, 2021, as Appl. No. 17/208,690.
Application 17/208,690 is a division of application No. 16/152,795, filed on Oct. 5, 2018, granted, now 10,971,765.
Prior Publication US 2021/0210796 A1, Jul. 8, 2021
Int. Cl. H10K 19/10 (2023.01); H01G 9/00 (2006.01); H01G 9/025 (2006.01); H01G 9/04 (2006.01); H01G 9/07 (2006.01); H01G 9/22 (2013.01); H01G 9/26 (2006.01); H01G 9/28 (2006.01); H01M 10/42 (2006.01); H10K 10/46 (2023.01); H10K 10/82 (2023.01); H10K 85/10 (2023.01); H01L 31/053 (2014.01)
CPC H10K 19/10 (2023.02) [H01G 9/0029 (2013.01); H01G 9/0036 (2013.01); H01G 9/025 (2013.01); H01G 9/04 (2013.01); H01G 9/07 (2013.01); H01G 9/22 (2013.01); H01G 9/26 (2013.01); H01G 9/28 (2013.01); H01M 10/4257 (2013.01); H10K 10/46 (2023.02); H10K 10/82 (2023.02); H10K 85/1135 (2023.02); H01L 31/053 (2014.12); H01M 2010/4271 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A method, comprising:
depositing a first insulator layer on a current collector layer in a first striped pattern;
depositing a channel semiconductor layer in a pattern such that multiple discrete regions of the channel semiconductor layer are disposed over first non-insulated portions of the current collector layer;
depositing a solid state electrolyte layer in a pattern of multiple discrete regions such that each discrete region of the solid state electrolyte contacts a region of the channel semiconductor layer;
depositing a layer of conductive material in discrete regions such that each discrete region of the conductive material layer makes contact with a discrete region of the channel semiconductor layer; and
depositing a gate electrode layer in a pattern of discrete regions such that each discrete region of the gate electrode layer contacts a discrete region of the solid state electrolyte layer and a discrete region of the conductive material layer or the current collector layer.