US 12,256,568 B2
Semiconductor structure having two N-type devices and two P-type devices and manufacturing method thereof
Xiaojie Li, Hefei (CN); and Mengmeng Yang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Apr. 4, 2022, as Appl. No. 17/657,875.
Claims priority of application No. 202110963282.5 (CN), filed on Aug. 20, 2021.
Prior Publication US 2023/0057058 A1, Feb. 23, 2023
Int. Cl. H10D 84/03 (2025.01); H01L 21/28 (2025.01); H01L 21/3213 (2006.01); H10D 30/69 (2025.01); H10D 64/66 (2025.01); H10D 84/01 (2025.01); H10D 84/85 (2025.01)
CPC H10D 84/038 (2025.01) [H01L 21/28088 (2013.01); H01L 21/32134 (2013.01); H01L 21/32135 (2013.01); H01L 21/32139 (2013.01); H10D 30/751 (2025.01); H10D 64/667 (2025.01); H10D 84/0167 (2025.01); H10D 84/0177 (2025.01); H10D 84/856 (2025.01)] 13 Claims
OG exemplary drawing
 
1. A manufacturing method of a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first N-type region of a first N-type device, a first P-type region of a first P-type device, a second N-type region of a second N-type device and a second P-type region of a second P-type device, wherein the first P-type region is adjacent to the first N-type region and the second N-type region, and the second N-type region is adjacent to the first P-type region and the second P-type region;
forming a strain layer on the substrate of the first P-type region;
forming an interface layer on the substrate of the first N-type region, the second N-type region, the second P-type region and on the strain layer of the first P-type region,
forming a high-K gate dielectric layer on the interface layer, wherein the interface layer and the high-K gate dielectric layer together form a fate dielectric layer, and wherein the high-K gate dielectric layer has a dielectric constraint greater than that of SiO2,
forming a first barrier layer on the gate dielectric layer, a first work function layer on the first barrier layer and a second barrier layer on the first work function layer on the substrate in sequence;
forming a mask layer on the second barrier layer of the first P-type region and the second P-type region;
removing the second barrier layer of the first N-type region and the second N-type region by a first etching process with the mask layer as a mask, so as to expose the first work function layer of the first N-type region and the second N-type region; and
removing the first work function layer and the first barrier layer of the first N-type region and the second N-type region by a second etching process, so as to expose the gate dielectric layer of the first N-type region and the second N-type region;
wherein a thickness of the interface layer of the second N-type region is greater than that of the interface layer of the first N-type region, and a thickness of the interface layer of the second P-type region is greater than that of the interface layer of the first P-type region.