| CPC H10D 64/258 (2025.01) [H10D 30/0321 (2025.01); H10D 30/6713 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 64/01 (2025.01)] | 14 Claims |
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1. A semiconductor device, comprising:
an active pattern extending in a first direction on a substrate;
a pair of source/drain patterns provided on the active pattern and spaced apart from each other in the first direction;
a plurality of channel layers stacked on the active pattern to be vertically spaced apart from each other and connecting the pair of source/drain patterns with each other;
a gate electrode provided at the active pattern between the pair of source/drain patterns, wherein the gate electrode extends in a second direction intersecting the first direction and surrounds each of the plurality of channel layers; and
a pair of active contacts provided at opposite sides of the gate electrode, respectively,
wherein each active contact of the pair of active contacts covers inclined top surfaces, relative to a top surface of the substrate, of a corresponding source/drain pattern of the pair of source/drain patterns, respectively,
wherein the inclined top surfaces are spaced apart from each other in the second direction,
wherein a width, in the second direction, of each of the pair of active contacts is smaller than or equal to a maximum width, in the second direction, of the corresponding source/drain pattern of the pair of source/drain patterns, and
wherein each of the pair of active contacts comprises protruding portions that protrudes toward and extends along the inclined top surfaces of the corresponding source/drain pattern of the pair of source/drain patterns.
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