| CPC H10D 62/151 (2025.01) [H10D 30/60 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 30/797 (2025.01); H10D 62/822 (2025.01); H10D 64/017 (2025.01); H10D 84/017 (2025.01); H10D 84/0172 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01)] | 20 Claims |
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1. A method of fabricating a semiconductor device, the method comprising:
forming an active pattern including sacrificial layers and active layers that are alternately stacked on a substrate in a vertical direction;
forming a liner layer on the active pattern;
forming a recess in an upper portion of the active pattern;
forming a first semiconductor layer in the recess by performing a first selective epitaxial growth process, the first semiconductor layer being grown using the active layers and the liner layer as seed layers; and
forming a second semiconductor layer in the recess by performing a second selective epitaxial growth process.
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