US 12,256,562 B1
Manufacturing method for a power MOSFET with gate-source ESD diode structure
Wan-Yu Kai, New Taipei (TW); Chia-Wei Hu, New Taipei (TW); and Ta-Chuan Kuo, New Taipei (TW)
Assigned to Diodes Incorporated, Plano, TX (US)
Filed by Diodes Incorporated, Plano, TX (US)
Filed on Jun. 20, 2024, as Appl. No. 18/749,576.
Application 18/749,576 is a division of application No. 18/416,776, filed on Jan. 18, 2024, granted, now 12,154,941.
Int. Cl. H01L 29/861 (2006.01); H10D 30/66 (2025.01); H10D 62/10 (2025.01); H10D 64/27 (2025.01); H10D 89/60 (2025.01)
CPC H10D 62/109 (2025.01) [H10D 30/668 (2025.01); H10D 64/513 (2025.01); H10D 89/611 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
growing an epitaxial layer over a substrate;
forming a plurality of gates in the epitaxial layer;
forming a source in the epitaxial layer;
forming a breakdown voltage enhancement and leakage prevention structure in the epitaxial layer, comprising a body ring structure;
forming a gate-source Electrostatic Discharge (ESD) diode structure over the epitaxial layer, wherein the gate-source ESD diode structure comprises a first p-type region, a second p-type region, and a third p-type region; and
forming a source contact connected to the source and a first terminal of the gate-source ESD diode structure, and a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, wherein the body ring structure comprises a plurality of rectangles:
in a cross-sectional view, the plurality of rectangles of the body ring structure comprises at least a first column, a second column, and a third column, with one sidewall of the first column is vertically aligned with a first sidewall of the first p-type region, one sidewall of the second column is vertically aligned with a second sidewall of the second p-type region, and one sidewall of the third column is vertically aligned with a third sidewall of the third p-type region, respectively.