US 12,256,558 B2
Technologies for fabricating a 3D memory structure
Sang Cheol Han, Albany, NY (US); Sunghil Lee, Albany, NY (US); Iljung Park, Boise, ID (US); and Soo Doo Chae, Albany, NY (US)
Assigned to Tokyo Electron Limited, Tokyo (JP)
Filed by Tokyo Electron Limited, Tokyo (JP)
Filed on Feb. 10, 2022, as Appl. No. 17/668,719.
Claims priority of provisional application 63/273,036, filed on Oct. 28, 2021.
Prior Publication US 2023/0133927 A1, May 4, 2023
Int. Cl. H10B 69/00 (2023.01); H01L 21/304 (2006.01); H01L 21/768 (2006.01)
CPC H10B 69/00 (2023.02) [H01L 21/76898 (2013.01); H01L 21/304 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method for forming a three-dimensional (3D) memory structure, the method comprising:
forming a memory array stack on a first side of a substrate, wherein the memory array stack includes multiple layers of memory cells and a top side opposite the substrate;
forming a far-back-end-of-the-line (FBEOL) structure on the top side of the memory array stack, wherein the FBEOL structure includes a first plurality of metallization layers;
forming a logic circuit layer on a second side of the substrate, wherein the logic circuit layer includes a plurality of logic transistors;
forming a back-end-of-the-line (BEOL) structure on the logic circuit structure, wherein the BEOL structure includes a second plurality of metallization layers: and
annealing the memory array stack prior to forming the FBEOL structure on the top side of the memory array stack.