US 12,256,555 B2
Memory device, semiconductor device, and method of fabricating semiconductor device
Carlos H. Diaz, Los Altos Hills, CA (US); Shy-Jay Lin, Hsinchu County (TW); and Ming-Yuan Song, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 12, 2023, as Appl. No. 18/333,498.
Application 18/333,498 is a continuation of application No. 17/319,115, filed on May 13, 2021, granted, now 11,716,859.
Prior Publication US 2023/0329005 A1, Oct. 12, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 61/00 (2023.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01)
CPC H10B 61/20 (2023.02) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10N 50/01 (2023.02); H10N 50/80 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor substrate comprising a transistor; and
an interconnect structure disposed over the semiconductor substrate, wherein the interconnect structure comprises:
a plurality of interlayer dielectric layers over the semiconductor substrate;
a first via surrounded by at least two interlayer dielectric layers among the plurality of interlayer dielectric layers and electrically connected with the transistor;
a memory cell disposed over the at least two interlayer dielectric layers among the plurality of interlayer dielectric layers and electrically connected with the first via; and
a first signal line embedded in a first middle interlayer dielectric layer among the plurality of interlayer dielectric layers, wherein the first signal line extends on the semiconductor substrate along a first direction, and along a thickness direction perpendicular to the first direction, a vertical projection of the first signal line is not overlapped with a vertical projection of the memory cell.