US 12,256,553 B2
On-die formation of single-crystal semiconductor structures
Jeffery Brandt Hull, Boise, ID (US); Anish A. Khandekar, Boise, ID (US); Hung-Wei Liu, Meridian, ID (US); and Sameer Chhajed, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 8, 2023, as Appl. No. 18/144,708.
Application 18/144,708 is a division of application No. 17/397,725, filed on Aug. 9, 2021, granted, now 11,683,937.
Prior Publication US 2023/0276635 A1, Aug. 31, 2023
Int. Cl. H10B 53/20 (2023.01); H01L 21/02 (2006.01)
CPC H10B 53/20 (2023.02) [H01L 21/02488 (2013.01); H01L 21/02532 (2013.01); H01L 21/0257 (2013.01); H01L 21/02592 (2013.01); H01L 21/02595 (2013.01); H01L 21/02645 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a deck of memory cells:
a dielectric portion above the deck of memory cells;
a semiconductor portion above the dielectric portion and comprising a plurality of single crystal patches each having a bottom surface in contact with a flat top surface of the dielectric portion; and
a plurality of transistors coupled with the deck of memory cells, wherein each transistor of the plurality of transistors comprises:
a first terminal in contact with a respective first doped portion of one of the plurality of single crystal patches;
a second terminal in contact with a respective second doped portion of the one of the plurality of single crystal patches; and
a gate conductor operable to modulate a conductivity of a respective third doped portion of the one of the plurality of single crystal patches that is between the respective first doped portion and the respective second doped portion.