US 12,256,551 B2
Method for forming semiconductor memory structure
Nuo Xu, Milpitas, CA (US); Sai-Hooi Yeong, Hsinchu County (TW); Yu-Ming Lin, Hsinchu (TW); and Zhiqiang Wu, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Nov. 20, 2022, as Appl. No. 18/057,225.
Application 18/057,225 is a division of application No. 17/142,166, filed on Jan. 5, 2021, granted, now 11,508,754.
Prior Publication US 2023/0083447 A1, Mar. 16, 2023
Int. Cl. H01L 29/78 (2006.01); G11C 11/22 (2006.01); G11C 16/04 (2006.01); H01L 27/06 (2006.01); H01L 29/66 (2006.01); H10B 51/00 (2023.01); H10B 51/30 (2023.01)
CPC H10B 51/30 (2023.02) [G11C 11/223 (2013.01); G11C 16/0466 (2013.01); G11C 16/0483 (2013.01); H01L 27/0688 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09); H10B 51/00 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor memory structure, comprising:
forming a plurality of doped regions separated from each other in a semiconductor substrate;
forming a stack comprising a plurality of first insulating layers and a plurality of second insulating layers alternately arranged over the semiconductor substrate;
forming a first trench in the stack;
replacing the plurality of second insulating layers with a plurality of conductive layers;
forming a second trench in the stack;
forming a charge-trapping layer and a channel layer in the second trench, wherein the charge-trapping layer is in physical contact with the semiconductor substrate and separated from the plurality of doped regions;
forming an isolation structure filling the second trench, wherein sidewalls of the isolation structure are in contact with the channel layer, and a bottom of the isolation structure is in contact with the charge-trapping layer; and
forming a source structure and a drain structure at two sides of the isolation structure.