US 12,256,550 B2
Three-dimensional memory device and method
Bo-Feng Young, Taipei (TW); Meng-Han Lin, Hsinchu (TW); Chih-Yu Chang, New Taipei (TW); Sai-Hooi Yeong, Zhubei (TW); and Yu-Ming Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 1, 2023, as Appl. No. 18/327,439.
Application 18/327,439 is a division of application No. 17/193,331, filed on Mar. 5, 2021, granted, now 11,716,856.
Prior Publication US 2023/0309315 A1, Sep. 28, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 51/20 (2023.01); H01L 21/02 (2006.01); H01L 23/522 (2006.01); H01L 29/24 (2006.01); H10B 51/30 (2023.01)
CPC H10B 51/20 (2023.02) [H01L 21/02565 (2013.01); H01L 23/5226 (2013.01); H01L 29/24 (2013.01); H10B 51/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
patterning a first trench extending through a first conductive line;
depositing a memory film along sidewalls and a bottom surface of the first trench;
depositing a channel layer over the memory film, the channel layer extending along the sidewalls and the bottom surface of the first trench;
depositing a first dielectric layer over and contacting the channel layer to fill the first trench;
patterning a first opening, wherein patterning the first opening comprises etching the first dielectric layer, and wherein patterning the first opening further comprises etching the channel layer;
depositing a gate dielectric layer in the first opening; and
depositing a gate electrode over the gate dielectric layer and in the first opening, the gate electrode being surrounded by the gate dielectric layer.