US 12,256,549 B2
Boundary design to reduce memory array edge CMP dishing effect
Wei Cheng Wu, Zhubei (TW); and Chien-Hung Chang, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 18, 2022, as Appl. No. 17/866,922.
Application 17/866,922 is a continuation of application No. 16/695,475, filed on Nov. 26, 2019, granted, now 11,424,263.
Application 16/695,475 is a continuation of application No. 16/033,357, filed on Jul. 12, 2018, granted, now 10,515,977, issued on Dec. 24, 2019.
Claims priority of provisional application 62/537,131, filed on Jul. 26, 2017.
Prior Publication US 2022/0359558 A1, Nov. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 43/50 (2023.01); H01L 21/76 (2006.01); H01L 21/762 (2006.01); H01L 29/06 (2006.01); H10B 43/40 (2023.01); H10B 43/10 (2023.01)
CPC H10B 43/50 (2023.02) [H01L 21/76 (2013.01); H01L 21/76224 (2013.01); H01L 29/0649 (2013.01); H10B 43/40 (2023.02); H10B 43/10 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a plurality of transistor devices disposed on or within a substrate;
a plurality of memory devices disposed on or within the substrate;
a first isolation structure disposed within the substrate between the plurality of transistor devices and the plurality of memory devices; and
a dummy gate structure arranged on the first isolation structure and having a top surface that is vertically above top surfaces of the plurality of transistor devices and the plurality of memory devices.