US 12,256,548 B2
Semiconductor device and method for manufacturing the same
Chen-Yu Cheng, Hsinchu (TW); and Tzung-Ting Han, Hsinchu (TW)
Assigned to MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed by MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed on May 19, 2022, as Appl. No. 17/748,121.
Prior Publication US 2023/0413548 A1, Dec. 21, 2023
Int. Cl. H01L 27/11578 (2017.01); H01L 27/11565 (2017.01); H10B 43/10 (2023.01); H10B 43/20 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01); H10B 43/50 (2023.01)
CPC H10B 43/50 (2023.02) [H10B 43/10 (2023.02); H10B 43/20 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a circuit board, comprising a plurality of circuit structures and a plurality of wires, the circuit structures being electrically connected to corresponding wires, and the circuit board having a peripheral area, an array area, and a staircase area disposed between the peripheral area and the array area;
a bottom plate, disposed over the circuit board, and the bottom plate comprising a bottom conductive layer;
a plurality of landing pads embedded in at least a top portion of the bottom conductive layer and contacting the bottom conductive layer in the staircase area;
a stack, disposed on the bottom plate, and the stack comprising a plurality of conductive layers and a plurality of insulating layers alternately stacked along a first direction;
a plurality of support pillars, passing through the stack along the first direction and extending to the landing pads in the staircase area; and
a plurality of memory pillars, passing through the stack along the first direction in the array area;
wherein the bottom conductive layer comprises a plurality of top openings in a top portion of the bottom conductive layer in the staircase area, and the landing pads are formed within the top openings of the bottom conductive layer.