US 12,256,547 B2
Silicon oxide nitride tunnel dielectric for a storage transistor in a 3-dimensional NOR memory string array
Scott Brad Herner, Portland, OR (US); Christopher J. Petti, Mountain View, CA (US); George Samachisa, Atherton, CA (US); and Wu-Yi Henry Chien, San Jose, CA (US)
Assigned to SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed by SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed on Oct. 5, 2021, as Appl. No. 17/494,549.
Application 17/494,549 is a continuation in part of application No. 17/155,673, filed on Jan. 22, 2021, granted, now 11,515,432.
Claims priority of provisional application 62/992,754, filed on Mar. 20, 2020.
Claims priority of provisional application 62/964,472, filed on Jan. 22, 2020.
Prior Publication US 2022/0028871 A1, Jan. 27, 2022
Int. Cl. H10B 43/35 (2023.01); G11C 16/04 (2006.01); H10B 43/20 (2023.01)
CPC H10B 43/35 (2023.02) [G11C 16/0483 (2013.01); H10B 43/20 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A storage transistor having a tunnel dielectric layer within the gate dielectric layer, wherein the tunnel dielectric layer comprises both a silicon oxide nitride (SiON) layer and an amorphous-phase aluminum oxide (Al2O3) layer, wherein the storage transistor further comprises a charge-trapping layer having a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer.