| CPC H10B 43/27 (2023.02) [H01L 29/42324 (2013.01); H01L 29/4234 (2013.01); H10B 41/27 (2023.02)] | 20 Claims |
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1. A semiconductor device, comprising:
a first semiconductor structure comprising a first substrate, circuit devices on the first substrate, and circuit interconnection lines electrically connected to the circuit devices; and
a second semiconductor structure on the first semiconductor structure,
wherein the second semiconductor structure comprises:
a second substrate having a first region and a second region;
gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate, and extend at different lengths in a second direction on the second region, and comprising pad regions having upper surfaces exposed on the second region;
interlayer insulating layers alternately stacked with the gate electrodes;
channel structures on the first region which penetrate the gate electrodes and extend in the first direction, wherein each of the channel structures comprises a channel layer;
contact plugs that are connected to the pad regions of the gate electrodes, extend in the first direction, and penetrate the pad regions; and
contact insulating layers below the pad regions and respectively surrounding the contact plugs,
wherein the pad regions of the gate electrodes have a first thickness and other regions of the gate electrodes have a second thickness less than the first thickness, and
wherein the contact plugs contact portions of upper surfaces, side surfaces, and lower surfaces of respective ones of the pad regions.
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