| CPC H10B 43/27 (2023.02) [H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10D 30/6735 (2025.01)] | 8 Claims |
|
1. A memory device comprising:
a dielectric substrate comprising an array region and a staircase region;
a memory array comprising:
a gate stack structure comprising a plurality of gate layers and a plurality of insulating layers alternately disposed above the dielectric substrate in the array region and the staircase region;
a plurality of first vertical transistors, stacked on each other and disposed above the dielectric substrate in the staircase region, comprising:
a plurality of first wraparound gate layers separated from each other and laterally adjacent to the gate stack structure;
a channel pillar extending through the first wraparound gate layers;
a gate dielectric layer disposed between the channel pillar and the first wraparound gate layers;
a first source/drain region located below a bottom of the channel pillar and electrically connected to the bottom of the channel pillar; and
a second source/drain region located above a top of the channel pillar and electrically connected to the top of the channel pillar,
wherein the memory device further comprises:
a first interconnect located below the first source/drain region and electrically connected to the first source/drain region;
a second interconnect located above the second source/drain region and electrically connected to the second source/drain region and one of the plurality of gate layers of the gate stack structure;
at least one second vertical transistor disposed in the staircase region and adjacent to the first vertical transistors; and
a common gate slit located between the first vertical transistors and the at least one second vertical transistor, and electrically connecting the first wraparound gate layers of the first vertical transistors and a second wraparound gate layer of the at least one second vertical transistor,
wherein the first interconnect is further connected to a third source/drain region of the second vertical transistor, and the second interconnect is further connected to a fourth source/drain region of the second vertical transistor.
|